400 Chapter7
ADC/Interface Section
A16 Assembly Fast ADC Control Circuits (8560E with Option 007)
video trigger level. The video trigger level value on IOB2 through IOB7
is latched into the P input (top portion of U34) by the firmware on the
A2 controller assembly when the fast ADC is in "read" mode. When the
sample on the Q input is higher than the video trigger level on the P
input, V_HI output is high, and V_LO output is low. When the Q input
is lower than the P input, V_HI output is low and V_LO output is high.
And when P is equal to Q, both V_HI and V_LO are low. These two
signals (V_HI and V_LO) go to PAL U1 (block A) and are used to clock
the video trigger generator (block D).
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