530 Chapter10
Synthesizer Section
Unlocked Reference PLL (600 MHz SAWR)
Check 10 MHz reference to phase/frequency detector (steps
8-13)
8. On the HP 8560E/EC, press
AUX CTRL, REAR PANEL, and 10 MHz
INT.
9. Check the 10 MHz reference frequency accuracy by connecting a
frequency counter to A15J301 and verify that the reference
frequency is 10 MHz ±40 Hz after a 5 minute warm-up period.
10.If a 10 MHz signal >1 V peak-to-peak is not present at A15J301,
refer to the "10 MHz Reference" in Chapter 11.
11.Measure the signal on U504 pin 3 with an oscilloscope. Refer to
function block O of A15 RF schematic.
12.Measure the signal at U504 pin 11 with an oscilloscope. Refer to
function block O of A15 RF schematic. This signal should be TTL
levels at 10 MHz with a 90 percent duty cycle.
13.If TTL-level signals (approximately 10 MHz) are not present, check
signals backwards through the loop to find a fault in the signal path.
14.Use an oscilloscope to check for 50 MHz TTL level signal at U503 pin
2. Refer to function block X of A15 RF schematic.
15.Measure the signals at the following test points with an active
probe/spectrum analyzer combination such as an HP 85024A/HP
8566A/B. The signal level at TP701 should be sufficient to drive an
ECL input.
16.If an approximately 10 MHz TTL signal is present at U504 pin 11
with 90 percent duty cycle, and the RF portion of the phase-lock loop
is functioning, the fault probably lies in the phase/frequency detector
or the 600 MHz reference loop amplifier.
Check phase/frequency detector (steps 17-22)
17.Monitor U504 pins 5 and 9 with an oscilloscope. These are the two
outputs of the phase/frequency detector. Refer to function block O of
A15 RF schematic.
18.A locked loop will exhibit stable, narrow (approximately 20 ns wide),
and positive-going TTL pulses occurring at a 10 MHz rate at U504
pins 5 and 9.
U502 pin 2 50 MHz, ≥+3 dBm
U502 pin 15 300 MHz, ≥+3 dBm
TP503 300 MHz, approximately +8 dBm
TP502 300 MHz (ECL level), approximately +3 dBm
TP701 600 MHz (ECL level), approximately +3 dBm
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