43 | P a g e
/* CPUPM POST code - Major */
#define STS_PPM_STRUCT_INIT 0xD0 // CPU PM Structure Init
#define STS_PPM_CSR_PROGRAMMING 0xD1 // CPU PM CSR programming
#define STS_PPM_MSR_PROGRAMMING 0xD2 // CPU PM MSR programming
#define STS_PPM_PSTATE_TRANSITION 0xD3 // CPU PM PSTATE transition
#define STS_PPM_EXIT 0xD4 // CPU PM driver exit
#define STS_PPM_ON_READY_TO_BOOT 0xD5 // CPU PM On ready to boot event
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