Hypertec CIARA ORION HF310-G4 - RC Debug Codes

42 | P a g e
24. RC_Debug code:
Major Checkpoint progress indicators written to debug port
#define STS_DIMM_DETECT 0xB0
#define STS_CLOCK_INIT 0xB1
#define STS_SPD_DATA 0xB2
#define STS_GLOBAL_EARLY 0xB3
#define STS_RANK_DETECT 0xB4
#define STS_CHANNEL_EARLY 0xB5
#define STS_DDRIO_INIT 0xB6
#define STS_CHANNEL_TRAINING 0xB7
#define STS_INIT_THROTTLING 0xB8
#define STS_MEMBIST 0xB9
#define STS_MEMINIT 0xBA
#define STS_DDR_MEMMAP 0xBB
#define STS_RAS_CONFIG 0xBC
#define STS_GET_MARGINS 0xBD
#define SSA_API_INIT 0xBE
#define STS_MRC_DONE 0xBF
#define STS_JEDEC_INIT 0xC0
==================================================================================================
================================== IIO POST code - Major Definitions ========================
==================================================================================================
**/
#define STS_IIO_EARLY_INIT_ENTRY 0xE0 // IIO early init entry
#define STS_EARLY_PRELINK_TRAINING 0xE1 // Early Pre-link training setting
#define STS_GEN3_EQ_PROGRAMMING 0xE2 // IIO Gen3 EQ programming
#define STS_LINK_TRAINING 0xE3 // IIO Link training
#define STS_GEN3_OVERRIDE 0xE4 // IIO Gen3 override
#define STS_IIO_EARLY_INIT_EXIT 0xE5 // IIO early init exit
#define STS_IIO_LATE_INIT_ENTRY 0xE6 // IIO late init entry
#define STS_IIO_PCIE_PORT_INIT 0xE7 // PCIE port init
#define STS_IIO_IOAPIC_INIT 0xE8 // IOAPIC init
#define STS_IIO_VTD_INIT 0xE9 // VTD init
#define STS_IIO_IOAT_INIT 0xEA // IOAT init
#define STS_IIO_DFX_INIT 0xEB // IIO DFX init
#define STS_IIO_NTB_INIT 0xEC // NTB init
#define STS_IIO_SECURITY_INIT 0xED // Security init
#define STS_IIO_LATE_INIT_EXIT 0xEE // IIO late init exit
#define STS_IIO_ON_READY_TO_BOOT 0xEF // IIO On ready to boot