Infineon TRAVEO T2G family CYT4D Series - Page 19

Application Note 19 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuration of the clock resources
Code Listing 8 Cy_SysClk_SelectEcoGtrim() function
}
else if(gm_min < 6.6f)
{
return(0x02ul+1ul);
}
else if(gm_min < 8.8f)
{
return(0x03ul+1ul);
}
else if(gm_min < 11.0f)
{
return(0x04ul+1ul);
}
else if(gm_min < 13.2f)
{
return(0x05ul+1ul);
}
else if(gm_min < 15.4f)
{
return(0x06ul+1ul);
}
else if(gm_min < 17.6f)
{
// invalid input
return(CY_SYSCLK_INVALID_TRIM_VALUE);
}
else
{
// invalid input
return(CY_SYSCLK_INVALID_TRIM_VALUE);
}
}
Code Listing 9 Cy_SysClk_SelectEcoRtrim() function
__STATIC_INLINE uint32_t Cy_SysClk_SelectEcoRtrim(float32_t freqMHz)
{
if(freqMHz > 28.6f)
{
return(0x00ul);
}
else if(freqMHz > 23.33f)
{
return(0x01ul);
}
else if(freqMHz > 16.5f)
{
return(0x02ul);
}
else if(freqMHz > 0.0f)
{
return(0x03ul);
}
else
{
// invalid input
return(CY_SYSCLK_INVALID_TRIM_VALUE);
}
}
Code Listing 10 Cy_SysClk_SelectEcoFtrim() function
__STATIC_INLINE uint32_t Cy_SysClk_SelectEcoFtrim(uint32_t atrim)
{
return(0x03ul);
}
Get the Rtrim value.
Get the Ftrim value.