Application Note 62 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuring the internal clock
5.11.2 Configuration
Table 21 lists the parameters and Table 22 lists the functions of the configuration part of in the SDL for LPECO
prescaler settings.
Table 21 List of LPECO prescaler settings parameters
LPECO_PRESCALER_TARGET_FR
EQ
ECO prescaler target frequency
Waiting for stabilization
PATH source clock frequency
Table 22 List of LPECO prescaler settings functions
Cy_SysClk_ClkBak_LPECO_Set
Prescale(frac,int)
Prescaler integer and
fractional divider to
generate 32.768 kHz from
the LPECO
frac = fixedPointDivNum & 0x000000FFul
int = (fixedPointDivNum & 0x0003FF00ul) >>
8ul) - 1ul
Cy_SysClk_ClkBak_LPECO_Ena
bleDivider(divInt,divFract
)
Set the prescaler enable for
the LPECO.
divInt = 0x3FF
divFract = 0xFF
Cy_SysClk_ClkBak_LPECO_Pre
scalerOkay()
Return the status from the
LPECO after setting the
prescaler divider.
5.11.3 Sample code for the initial configuration of LPECO prescaler settings
Code Listing 51 to Code Listing 55 show the sample code.
Code Listing 51 General configuration of LPECO prescaler settings
#define LPECO_PRESCALER_TARGET_FREQ (1234567ul)
#define CLK_FREQ_LPECO (8000000ul)
#define PATH_SOURCE_CLOCK_FREQ CLK_FREQ_LPECO
/** Wait time definition **/
#define WAIT_FOR_STABILIZATION (10000ul)
int main(void)
{
:
/* Set Clock Configuring registers */
AllClockConfiguration();
:
/* Please check clock output using oscilloscope after CPU reached here. */
for(;;);
}
Define the LPECO prescaler target frequency.
LPECO prescaler setting. See Code Listing 52.
Define the LPECO clock frequency.
Define the TIMEOUT variable.