Infineon TRAVEO T2G family CYT4D Series - 4.1.2 Use case; 4.1.3 Configuration

Application Note 27 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuration of the FLL and PLL
4.1.2 Use case
• Input clock frequency: 16 MHz
• Output clock frequency: 100 MHz
4.1.3 Configuration
Table 7 lists the parameters and Table 8 lists the functions of the configuration part of in the SDL for FLL
settings.
Table 7 List of FLL settings parameters
Parameters
Description
Value
WAIT_FOR_STABILIZATION
Waiting for stabilization
10000ul
FLL_PATH_NO
FLL number
0u
FLL_TARGET_FREQ
FLL target frequency
100000000ul (100 MHz)
CLK_FREQ_ECO
Source clock frequency
16000000ul (16 MHz)
PATH_SOURCE_CLOCK_FREQ
Source clock frequency
CLK_FREQ_ECO
CY_SYSCLK_FLLPLL_OUTPUT_
AUTO
FLL output mode
CY_SYSCLK_FLLPLL_OUTPUT_AUTO:
Automatic using the lock indicator.
CY_SYSCLK_FLLPLL_OUTPUT_LOCKED_OR_
NOTHING:
Similar to AUTO, except that the clock is gated
off when unlocked.
CY_SYSCLK_FLLPLL_OUTPUT_INPUT:
Select FLL reference input (bypass mode)
CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT:
Select the FLL output. Ignores the lock
indicator.
See SRSS_CLK_FLL_CONFIG3 in the registers
TRM for details.
0ul
Table 8 List of FLL settings functions
Functions
Description
Value
AllClockConfiguration()
Clock configuration
–
Cy_SysClk_FllConfigure
Standard(inputFreq,
outputFreq, outputMode)
inputFreq: Input frequency
inputFreq = PATH_SOURCE_
CLOCK_FREQ,
outputFreq: Output frequency
outputFreq = FLL_TARGET_FREQ,
outputMode: FLL output mode
outputMode = CY_SYSCLK_FLLPLL_
OUTPUT_AUTO
Cy_SysClk_FllEnable
(Timeout value)
Set FLL enable and timeout value
Timeout value =
WAIT_FOR_STABILIZATION
Cy_SysLib_DelayUs(Wait
Time)
Delay by the specified number of
microseconds
Wait time = 1u (1us)