Infineon TRAVEO T2G family CYT4D Series - 5.9 Configuring PCLK; 5.9.1 Example of PCLK setting; 5.9.1.1 Use case; 5.9.1.2 Configuration

Application Note 53 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuring the internal clock
5.9 Configuring PCLK
The PCLK is a clock that activates each peripheral function. Peripheral clock dividers have a function to divide
the CLK_PERI and generate a clock to be supplied to each peripheral function. For assignment of the peripheral
clocks, see the “Peripheral clocks” section in the datasheet.
Figure 17 shows the steps to configure peripheral clock dividers. See the architecture TRM for details.
Clock Divider 8.0
Clock Divider 16.0
Start
End
PERI_DIV_8_CTL.INT8_DIV=X_3
(X_3 = 0..255)
PERI_CLOCK_CTL.TYPE_SEL=X_2
(X_2 = 0, 1, 2, 3)
PERI_CLOCK_CTL.DIV_SEL=X_1
(X_1 = 0..255)
Select Clock Divider
Clock Divider 16.5
PERI_DIV_16_CTL.INT16_DIV=X_4
(X_4 = 0..65535)
PERI_DIV_16_5_CTL.INT16_DIV=X_6
(X_6 = 0..65535)
PERI_DIV_CMD.DIV_SEL=X_9
(X_9 = 0..255)
PERI_DIV_16_5_CTL.FRAC5_DIV=X_5
(X_5 = 0..31)
PERI_DIV_CMD.TYPE_SEL=X_10
(X_10 = 0, 1, 2, 3)
PERI_DIV_CMD.ENABLE=1
PERI_DIV_CMD.DISABLE=1
Configure the number of divisions using
"Clock Divider 8.0"
Disable the peripheral clock divider
Select DIV to use
Select TYPE to use
Select the clock divider to use
Configure the number of divisions using
"Clock Divider 16.0"
Configure the number of fractional divisions
using "Clock Divider 16.5"
Configure the number of integer divisions
using "Clock Divider 16.5"
Configure to use the configured DIV
Enable the peripheral clock divider
Configure to use the configured SEL
Note: If DIV_SEL is "63" and TYPE_SEL is "3" (default/reset value), no divider is specified and no clock signal(s) are generated.
PERI_DIV_8_CTL.EN=1
Enable "Clock Divider 8.0"
PERI_DIV_16_CTL.EN=1 Enable "Clock Divider 16.0"
PERI_DIV_16_5_CTL.EN=1 Enable "Clock Divider 16.5"
Clock Divider 24.5
PERI_DIV_24_5_CTL.INT24_DIV=X_8
(X_8 = 0..16777215 )
PERI_DIV_24_5_CTL.FRAC5_DIV=X_7
(X_7 = 0..31)
PERI_DIV_24_5_CTL.EN=1
Configure the number of fractional divisions
using "Clock Divider 24.5"
Configure the number of integer divisions
using "Clock Divider 24.5"
Enable "Clock Divider 24.5"
Figure 17 Procedure for configuring to generate the PCLK