Infineon TRAVEO T2G family CYT4D Series - 5.7 Configuring CLK_SLOW; 5.8 Configuring CLK_GR

Application Note 52 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuring the internal clock
5.7 Configuring CLK_SLOW
The CLK_SLOW is generated by dividing the CLK_MEM; its frequency is configured by the value obtained by
dividing CLK_MEM by (x+1). After configuring the CLK_MEM, configure a value divided (x= 0 to 255) by the
INT_DIV bit of the CPUSS_SLOW_CLOCK_CTL register.
5.8 Configuring CLK_GR
The clock source of the CLK_GP is the CLK_PERI in groups 3, 4, 8 and CLK_HF2 in groups 5, 6, 9. Groups 3, 4, 8
are clocks divided by CLK_PERI. To generate CLK_GR3, CLK_GR4, and CLK_GR8, write the division value (from 1
to 255) to divide the INT8_DIV bit of the CPUSS_PERI_GRx_CLOCK_CTL register.