Infineon TRAVEO T2G family CYT4D Series - 5.11 Configuring the LPECO_Prescaler; 5.11.1 Use case

Application Note 61 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuring the internal clock
5.11 Configuring the LPECO_Prescaler
The LPECO_Prescaler divides the LPECO. The division function has a 10-bit integer divider and 8-bit fractional
divider.
Figure 21 shows the steps to enable the LPECO_Prescaler. For details on the LPECO_Prescaler, see the
architecture TRM.
Start
LPECO prescaler enabled
Wait until LPECO prescaler is available?
No
End
Yes
Configure 8-bit fractional value
Configure 10-bit integer value
Note: Do not change the LPECO_FRAC_DIV and LPECO_INT_DIV settings when LPECO_DIV_ENABLE = 1.
(1)
(2)
(3)
Figure 21 Enabling the LPECO_Prescaler
Figure 22 shows the steps to disable the LPECO_Prescaler. For details on the LPECO_Prescaler, see the
architecture TRM.
Start
LPECO prescaler disabled
Wait until LPECO prescaler is unavailable?
No
End
Yes
(4)
(5)
Figure 22 Disabling the LPECO_Prescaler
5.11.1 Use case
• Input clock frequency: 8 MHz
• LPECO prescaler target frequency: 1.234567 MHz