Infineon TRAVEO T2G family CYT4D Series - 7 Glossary

Application Note 75 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Glossary
7 Glossary
Table 36 Glossary
Terms
Description
AUDIOSS
Audio subsystem. See the “Audio subsystem” chapter of TRAVEO™ T2G
architecture TRM for details.
CAN FD
CAN FD is the CAN with flexible data rate, and CAN is the controller area
network. See the “CAN FD controller” chapter of TRAVEO™ T2G architecture
TRM for details.
CLK_FAST_0
Fast clock. The CLK_FAST is used for the CM7 and CPUSS fast infrastructure.
CLK_FAST_1
Fast clock. The CLK_FAST is used for the CM7 and CPUSS fast infrastructure.
CLK_GR
Group clock. The CLK_GR is the clock input to peripheral functions.
CLK_HF
High-frequency clock. The CLK_HF derives both CLK_FAST and CLK_SLOW.
CLK_HF, CLK_FAST, and CLK_SLOW are synchronous to each other.
CLK_MEM
Memory clock. The CLK_MEM clocks the CPUSS fast infrastructure.
CLK_PERI
Peripheral clock. The CLK_PERI is the clock source for CLK_SLOW, CLK_GR and
peripheral clock divider.
CLK_SLOW
Slow clock. The CLK_FAST is used for the CM0+ and CPUSS slow infrastructure.
Clock Calibration Counter
Clock calibration counter has a function to calibrate the clock using two
clocks.
CSV
Clock supervision
CXPI
Clock extension peripheral interface. See the “Clock extension peripheral
interface (CXPI)” chapter of the TRAVEO™ T2G architecture TRM for details.
ECO
External crystal oscillator
EXT_CLK
External clock
FLL
Frequency-locked loop
FPU
Floating point unit
ILO
Internal low-speed oscillators
IMO
Internal main oscillator
LIN
Local interconnect network. See the “Local interconnect network (LIN)”
chapter of the TRAVEO™ T2G architecture TRM for details.
LPECO
Low-power external crystal oscillator
Peripheral clock divider
The peripheral clock divider derives a clock for use in each peripheral function.
PLL#0
Phase-locked loop. This PLL is not implemented with SSCG and fractional
operation.
PLL#1
Phase-locked loop. This PLL is not implemented with SSCG and fractional
operation.
PLL#2
Phase-locked loop. This PLL is implemented with SSCG and fractional
operation.
PLL#3
Phase-locked loop. This PLL is implemented with SSCG and fractional
operation.
SAR ADC
Successive approximation register analog-to-digital converter. See the “SAR
ADC” chapter of the TRAVEO™ T2G architecture TRM for details.