Application Note 76 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Serial communications block. See the “Serial communications block (SCB)”
chapter of the TRAVEO™ T2G architecture TRM for details.
Serial memory interface. See the “Serial memory interface” chapter of the
TRAVEO™ T2G architecture TRM for details.
Timer, counter, and pulse width modulator. See the “Timer, counter, and
PWM” chapter of the TRAVEO™ T2G architecture TRM for details.
Video subsystem. See the “Video subsystem” chapter of the TRAVEO™ T2G
architecture TRM for details.
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