Infineon TRAVEO T2G family CYT4D Series - 5.10 Setting ECO_Prescaler; 5.10.1 Use case; 5.10.2 Configuration

Application Note 57 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuring the internal clock
5.10 Setting ECO_Prescaler
The ECO_Prescaler divides the ECO, and creates a clock that can be used with the CLK_LF. The division function
has a 10-bit integer divider and 8-bit fractional divider.
Figure 19 shows the steps to enable the ECO_Prescaler. For details on the ECO_Prescaler, see the architecture
TRM and registers TRM.
Start
ECO prescaler enabled
Wait until ECO prescaler is available?
No
End
Yes
Configure 8-bit fractional value
Configure 10-bit integer value
Configure 8-bit fractional value
Configure 10-bit integer value
ECO prescaler enabled
Wait until ECO rescaler is available
Note: Do not change the ECO_FRAC_DIV and ECO_INT_DIV settings when ECO_DIV_ENABLE = 1.
Define ECO prescaler target frequency Set ECO prescaler target frequency
(1)
(2)
(3)
Figure 19 Enabling the ECO_Prescaler
Figure 20 shows the flow to disable the ECO_Prescaler. For details on the ECO_Prescaler, see the architecture
TRM.
Start
ECO prescaler disabled
Wait until ECO prescaler is unavailable?
No
End
Yes
ECO prescaler disabled
Wait until ECO prescaler is unavailable
(4)
(5)
Figure 20 Disabling the ECO_Prescaler