Infineon TRAVEO T2G family CYT4D Series - 5.3 Configuring the CLK_LF; 5.4 Configuring CLK_FAST_0;CLK_FAST_1; 5.5 Configuring CLK_MEM; 5.6 Configuring CLK_PERI

Application Note 51 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuring the internal clock
5.3 Configuring the CLK_LF
The CLK_LF can be selected from one of the possible sources WCO, ILO0, ILO1, ECO_Prescaler, and
LPECO_Prescaler. The CLK_LF cannot be configured when the WDT_LOCK bit in the WDT_CLTL register is
disabled because the CLK_LF can select the ILO0 that is the input clock for the WDT.
Figure 16 shows the details of LFCLK_SEL that configure the CLK_LF.
LFCLK_SEL
ILO0
CLK_LF
ILO1
WCO
ECO_Prescaler
LPECO_Prescaler
Figure 16 LFCLK_SEL
Table 16 shows the registers required for the CLK_LF. See the architecture TRM for details.
Table 16 Configuring of the CLK_LF
Register name
Bit name
Value
Selected item
CLK_SELECT
LFCLK_SEL[2:0]
0 (Default)
ILO0
1
WCO
4
ILO1
5
ECO_Prescaler
6
LPECO_Prescaler
other
Reserved. Do not use.
5.4 Configuring CLK_FAST_0/CLK_FAST_1
CLK_FAST_0 and CLK_FAST_1 are generated by dividing CLK_HF1 by (x+1). When configuring the CLK_FAST_0
and CLK_FAST_1, configure a value (x = 0 to 255) divided by the FRAC_DIV bit and INT_DIV bit of the
CPUSS_FAST_0_CLOCK_CTL register and CPUSS_FAST_1_CLOCK_CTL register.
5.5 Configuring CLK_MEM
The CLK_MEM is generated by dividing the CLK_HF0; its frequency is configured by the value obtained by
dividing the CLK_HF0 by (x+1). When configuring the CLK_MEM, configure a value (x= 0 to 255) divided by the
INT_DIV bit of the CPUSS_MEM_CLOCK_CTL register.
5.6 Configuring CLK_PERI
The CLK_PERI is the clock input to the peripheral clock divider and CLK_GR. The CLK_PERI is generated by
dividing the CLK_HF0; its frequency is configured by the value obtained by dividing CLK_HF0 by (x+1). When
configuring the CLK_PERI, configure a value (x= 0 to 255) divided by the INT_DIV bit of the
CPUSS_PERI_CLOCK_CTL register.