Infineon TRAVEO T2G family CYT4D Series - Use Case; Configuration

Application Note 58 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuring the internal clock
5.10.1 Use case
• Input clock frequency: 16 MHz
• ECO prescaler target frequency: 1.234567 MHz
5.10.2 Configuration
Table 19 lists the parameters and Table 20 lists the functions of the configuration part of in the SDL for ECO
prescaler settings.
Table 19 List of ECO prescaler settings parameters
Parameters
Description
Value
ECO_PRESCALER_TARGET_FREQ
ECO prescaler target frequency
1234567ul
WAIT_FOR_STABILIZATION
Waiting for stabilization
10000ul
CLK_FREQ_ECO
ECO clock frequency
16000000ul (16 MHz)
PATH_SOURCE_CLOCK_FREQ
PATH source clock frequency
CLK_FREQ_ECO
Table 20 List of ECO prescaler setting functions
Functions
Description
Value
AllClockConfiguration()
Clock configuration
–
Cy_SysClk_SetEco
Prescale(Inclk, Targetclk)
Set the ECO frequency and
target frequency.
Inclk = PATH_SOURCE_CLOCK_FREQ,
Targetclk =
ECO_PRESCALER_TARGET_FREQ
Cy_SysClk_EcoPrescale
Enable(Timeout value)
Set the ECO prescaler
enable and timeout value
Timeout value = WAIT_FOR_STABILIZATION
Cy_SysClk_SetEco
PrescaleManual (divInt,
divFact)
divInt: 10-bit integer value
allows for ECO frequencies
divFrac: 8-bit fractional
value
–
Cy_SysClk_GetEco
PrescaleStatus
Check the prescaler status.
–