Infineon TRAVEO T2G family CYT4D Series - 6.2.2 ILO0 calibration using the clock calibration counter function

Application Note 70 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Supplementary information
Code Listing 62 Cy_SysClk_ClkMeasurementCountersGetFreq() function
if(clk1Count1 == 0ul)
{
return(CY_SYSCLK_INVALID_STATE);
}
volatile uint64_t counter2Value = (uint64_t)SRSS->unCLK_CAL_CNT2.stcField.u24CAL_COUNTER2;
/* Done counting; allow entry into DeepSleep mode. */
clkCounting = false;
*measuredFreq = CY_SYSCLK_DIV_ROUND(counter2Value * (uint64_t)refClkFreq, (uint64_t)clk1Count1 );
return(CY_SYSCLK_SUCCESS);
}
6.2.2 ILO0 calibration using the clock calibration counter function
The ILO frequency is determined during manufacturing. Because the ILO frequency varies according to voltage
and temperature conditions, the ILO frequency can be updated in the field. The ILO frequency trim can be
updated using the ILOx_FTRIM bit of the CLK_TRIM_ILOx_CTL register. The initial value of the ILOx_FTRIM bit is
0x2C. Increasing the value of this bit by 0x01 increases the frequency by 1.5% (typical); decreasing this bit value
by 0x01 decreases the frequency by 1.5% (typical). The CLK_TRIM_ILO0_CTL register is protected by
WDT_CTL.WDT_LOCK. For the specification of the WDT_CTL register, see the “Watchdog timer” section of the
architecture TRM.
Figure 24 shows an example flow of ILO0 calibration using the clock calibration counter and the
CLK_TRIM_ILOx_CTL register.
Start
Disable watchdog timer
Get current ILO 0 frequency
Calculate the trimming step
Calculate difference frequency
between current and target
Define a target ILO 0 frequency
Define ILO number
Get current trimming value
Calculate new trimming value
Set new trimming value
End
(3)
(1)
(2)
(4)
(5)
(6)
(7)
Figure 24 ILO0 calibration
(6) Get the ILO 0 frequency.
Get the ILO 0 count value.