Infineon TRAVEO T2G family CYT4D Series - 4.2 Setting PLL

Application Note 31 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuration of the FLL and PLL
Code Listing 25 Cy_SysClk_FllEnable() function
cy_en_sysclk_status_t Cy_SysClk_FllEnable(uint32_t timeoutus)
{
/* first set the CCO enable bit */
SRSS->unCLK_FLL_CONFIG4.stcField.u1CCO_ENABLE = 1ul;
/* Wait until CCO is ready */
while(SRSS->unCLK_FLL_STATUS.stcField.u1CCO_READY == 0ul)
{
if(timeoutus == 0ul)
{
/* If cco ready doesn't occur, FLL is stopped. */
Cy_SysClk_FllDisable();
return(CY_SYSCLK_TIMEOUT);
}
Cy_SysLib_DelayUs(1u);
timeoutus--;
}
/* Set the FLL bypass mode to 2 */
SRSS->unCLK_FLL_CONFIG3.stcField.u2BYPASS_SEL = (uint32_t)CY_SYSCLK_FLLPLL_OUTPUT_INPUT;
/* Set the FLL enable bit, if CCO is ready */
SRSS->unCLK_FLL_CONFIG.stcField.u1FLL_ENABLE = 1ul;
/* now do the timeout wait for FLL_STATUS, bit LOCKED */
while(SRSS->unCLK_FLL_STATUS.stcField.u1LOCKED == 0ul)
{
if(timeoutus == 0ul)
{
/* If lock doesn't occur, FLL is stopped. */
Cy_SysClk_FllDisable();
return(CY_SYSCLK_TIMEOUT);
}
Cy_SysLib_DelayUs(1u);
timeoutus--;
}
/* Lock occurred; we need to clear the unlock occurred bit.
Do so by writing a 1 to it. */
SRSS->unCLK_FLL_STATUS.stcField.u1UNLOCK_OCCURRED = 1ul;
/* Set the FLL bypass mode to 3 */
SRSS->unCLK_FLL_CONFIG3.stcField.u2BYPASS_SEL = (uint32_t)CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT;
return(CY_SYSCLK_SUCCESS);
}
4.2 Setting PLL
The PLL must be configured before using it. Figure 13 shows the steps to configure PLL400 and PLL200. For
details on PLL400 and PLL200, see the architecture TRM.
(6) Enable the FLL.
Wait for 1 us.
(3) Enable the CCO.
(4) Wait until the CCO is available.
FLL disabled if timeout occurs.
FLL disabled if a timeout occurs.
Wait for 1 us.
(5) Check the timeout.
(8) Check the timeout.
(7) Wait until the FLL is locked.