Infineon TRAVEO T2G family CYT4D Series - Page 30

Application Note 30 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuration of the FLL and PLL
Code Listing 24 Cy_SysClk_FllManualConfigure() function
cy_en_sysclk_status_t Cy_SysClk_FllManualConfigure(const cy_stc_fll_manual_config_t *config)
{
cy_en_sysclk_status_t returnStatus = CY_SYSCLK_SUCCESS;
/* check for errors */
if (SRSS->unCLK_FLL_CONFIG.stcField.u1FLL_ENABLE != 0ul) /* 1 = enabled */
{
returnStatus = CY_SYSCLK_INVALID_STATE;
}
else
{ /* return status is OK */
}
/* no error */
if (returnStatus == CY_SYSCLK_SUCCESS) /* no errors */
{
/* update CLK_FLL_CONFIG register with 2 parameters; FLL_ENABLE is already 0 */
un_CLK_FLL_CONFIG_t tempConfg;
tempConfg.u32Register = SRSS->unCLK_FLL_CONFIG.u32Register;
tempConfg.stcField.u18FLL_MULT = config->fllMult;
tempConfg.stcField.u1FLL_OUTPUT_DIV = (uint32_t)(config->enableOutputDiv);
SRSS->unCLK_FLL_CONFIG.u32Register = tempConfg.u32Register;
/* update CLK_FLL_CONFIG2 register with 2 parameters */
un_CLK_FLL_CONFIG2_t tempConfg2;
tempConfg2.u32Register = SRSS->unCLK_FLL_CONFIG2.u32Register;
tempConfg2.stcField.u13FLL_REF_DIV = config->refDiv;
tempConfg2.stcField.u8LOCK_TOL = config->lockTolerance;
tempConfg2.stcField.u8UPDATE_TOL = config->updateTolerance;
SRSS->unCLK_FLL_CONFIG2.u32Register = tempConfg2.u32Register;
/* update CLK_FLL_CONFIG3 register with 4 parameters */
un_CLK_FLL_CONFIG3_t tempConfg3;
tempConfg3.u32Register = SRSS->unCLK_FLL_CONFIG3.u32Register;
tempConfg3.stcField.u4FLL_LF_IGAIN = config->igain;
tempConfg3.stcField.u4FLL_LF_PGAIN = config->pgain;
tempConfg3.stcField.u13SETTLING_COUNT = config->settlingCount;
tempConfg3.stcField.u2BYPASS_SEL = (uint32_t)(config->outputMode);
SRSS->unCLK_FLL_CONFIG3.u32Register = tempConfg3.u32Register;
/* update CLK_FLL_CONFIG4 register with 1 parameter; preserve other bits */
un_CLK_FLL_CONFIG4_t tempConfg4;
tempConfg4.u32Register = SRSS->unCLK_FLL_CONFIG4.u32Register;
tempConfg4.stcField.u3CCO_RANGE = (uint32_t)(config->ccoRange);
tempConfg4.stcField.u9CCO_FREQ = (uint32_t)(config->cco_Freq);
tempConfg4.stcField.u1CCO_HW_UPDATE_DIS = (uint32_t)(config->ccoHwUpdateDisable);
SRSS->unCLK_FLL_CONFIG4.u32Register = tempConfg4.u32Register;
} /* if no error */
return (returnStatus);
}
(2) FLL configuration
(1) Check if the FLL is already enabled.
Set the CLK_FLL_CONFIG register.
Set the CLK_FLL_CONFIG2 register.
Set the CLK_FLL_CONFIG3 register.
Set the CLK_FLL_CONFIG4 register.