Application Note 65 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Supplementary information
6 Supplementary information
6.1 Input clocks in peripheral functions
Table 23 to Table 30 list the clock input to each peripheral function. For detailed values of PCLK, see the
“Peripheral clocks” section of the datasheet.
Table 23 Clock input to TCPWM[0]
PCLK (PCLK_TCPWM0_CLOCKSx, x = 0 to 37)
PCLK (PCLK_TCPWM0_CLOCKSy, y = 256 to 267)
PCLK (PCLK_TCPWM0_CLOCKSz, z =512–543)
Table 24 Clock input to CAN FD
Operation clock
(clk_sys (hclk))
Channel clock (clk_can (cclk))
Ch0: PCLK (PCLK_CANFD0_CLOCK_CANFD0)
Ch1: PCLK (PCLK_CANFD0_CLOCK_CANFD1)
Ch0: PCLK (PCLK_CANFD1_CLOCK_CANFD0)
Ch1: PCLK (PCLK_CANFD1_CLOCK_CANFD1)
Table 25 Clock input to LIN
Channel clock (clk_lin_ch)
Ch0: PCLK (PCLK_LIN_CLOCK_CH_EN0)
Ch1: PCLK (PCLK_LIN_CLOCK_CH_EN1)
Table 26 Clock input to SCB
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