Infineon TRAVEO T2G family CYT4D Series - Page 64

Application Note 64 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuring the internal clock
Code Listing 55 Cy_SysClk_ClkBak_LPECO_PrescaleEnable() function
return CY_SYSCLK_TIMEOUT;
}
Cy_SysLib_DelayUs(1u);
timeoutus--;
}
return CY_SYSCLK_SUCCESS;
}
Code Listing 56 Cy_SysClk_ClkBak_LPECO_PrescalerOkay() function
__STATIC_INLINE bool Cy_SysClk_ClkBak_LPECO_PrescalerOkay(void)
{
if(BACKUP->unLPECO_PRESCALE.stcField.u1LPECO_DIV_ENABLED == 1)
{
return true;
}
else
{
return false;
}
}
To disable the LPECO prescaler, set the wait time in the same way as the function above, and then call the next
function.
Code Listing 57 Cy_SysClk_ClkBak_LPECO_PrescaleDisable() function
__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkBak_LPECO_PrescaleDisable(uint32_t timeoutus)
{
// Send the disable command
BACKUP->unLPECO_CTL.stcField.u1LPECO_EN = 0ul;
// Wait for eco prescaler to get enabled
while(BACKUP->unLPECO_PRESCALE.stcField.u1LPECO_DIV_ENABLED == 1)
{
if(0ul == timeoutus)
{
return CY_SYSCLK_TIMEOUT;
}
Cy_SysLib_DelayUs(1u);
timeoutus--;
}
return CY_SYSCLK_SUCCESS;
}
Check the prescaler status.
(4) Disable the LPECO prescaler.
(5) Wait until the LPECO prescaler
is unavailable.