Infineon TRAVEO T2G family CYT4D Series - 5.2 Configuring CLK_HFx

Application Note 50 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuring the internal clock
5.2 Configuring CLK_HFx
The CLK_HFx (x = 0 to 13) can be selected from CLK_PATHy (y= 0 to 9). A predivider is available to divide the
selected CLK_PATHx. The CLK_HF0 is always enabled because it is the source clock for the CPU cores. It is
possible to disable CLK_HFx.
To enable the CLK_HFx, write ‘1’ to the ENABLE bit of each CLK_ROOT_SELECT register. To disable CLK_HFx,
write ‘0’ to the ENABLE bit of each CLK_ROOT_SELECT register.
The ROOT_DIV bit of the CLK_ROOT register configures the predivider values from the following options: no
division, divide by 2, divide by 4, and by 8.
Figure 15 shows the details of the ROOT_MUX and predivider.
ROOT_MUX
Predivider
CLK_PATH1
CLK_HF0 / CLK_HF1 / CLK_HF2 / CLK_HF3 / CLK_HF4 /
CLK_HF5 / CLK_HF6 / CLK_HF7 / CLK_HF8 / CLK_HF9 /
CLK_HF10 / CLK_HF11 / CLK_HF12 / CLK_HF13
ROOT_DIV
CLK_PATH0
CLK_PATH3
CLK_PATH2
CLK_PATH5
CLK_PATH4
CLK_PATH7
CLK_PATH6
CLK_PATH9
CLK_PATH8
Figure 15 ROOT_MUX and predivider
Table 15 shows the registers required for the CLK_HFx. See the architecture TRM for details.
Table 15 Configuring of the CLK_HFx
Register name
Bit name
Value
Selected item
CLK_ROOT_SELECT
ROOT_MUX[3:0]
0
CLK_PATH0
1
CLK_PATH1
2
CLK_PATH2
3
CLK_PATH3
4
CLK_PATH4
5
CLK_PATH5
6
CLK_PATH6
7
CLK_PATH7
8
CLK_PATH8
9
CLK_PATH9
Other
Reserved. Do not use.
CLK_ROOT_SELECT
ROOT_DIV[1:0]
0
No division
1
Divide clock by 2
2
Divide clock by 4
3
Divide clock by 8