Infineon TRAVEO T2G family CYT4D Series - Page 49

Application Note 49 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuring the internal clock
Table 14 Configuring CLK_PATHx
Register name
Bit name
Value
Selected clock and item
CLK_PATH_SELECT
PATH_MUX[2:0]
0 (Default)
IMO
1
EXT_CLK
2
ECO
4
DSI_MUX
5
LPECO
other
Reserved. Do not use.
CLK_DSI_SELECT
DSI_MUX[4:0]
16
ILO0
17
WCO
20
ILO1
Other
Reserved. Do not use.
CLK_FLL_CONFIG3
BYPASS_SEL[29:28]
0 (Default)
AUTO
1
1
LOCKED_OR_NOTHING
2
2
FLL_REF (bypass mode)
3
3
FLL_OUT
3
CLK_PLL_CONFIG
BYPASS_SEL[29:28]
0 (Default)
AUTO
1
1
LOCKED_OR_NOTHING
2
2
PLL_REF (bypass mode)
3
3
PLL_OUT
3
1
Switching automatically according to the locked state.
2
The clock is gated off when unlocked.
3
In this mode, the lock state is ignored.