Infineon TRAVEO T2G family CYT4D Series - 4.2.1 Use case; 4.2.2 Configuration

Application Note 33 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuration of the FLL and PLL
4.2.1 Use case
• Input clock frequency: 16.000 MHz
• Output clock frequency:
250.000 MHz (PLL400 #0)
196.608 MHz (PLL400 #1)
160.000 MHz (PLL200 #0)
80.000 MHz (PLL200 #1)
• Fractional divider:
Disable (PLL400 #0)
Enable (PLL400 #1)
• SSCG:
Enable (PLL400 #0)
Disable (PLL400 #1)
• SSCG dithering:
Enable (PLL400 #0)
Disable (PLL400 #1)
• SSCG modulation depth: -2.0% (PLL400)
• SSCG modulation rate: Divide 512 (PLL400)
• LF mode: 200 MHz to 400 MHz (PLL200)
4.2.2 Configuration
Table 9 and Table 11 list parameters of the PLL (400/200); Table 10 and Table 12 list functions of the PLL
(400/200) of the configuration part of in the SDL for PLL (400/200) settings.
Table 9 List of PLL 400 settings parameters
Parameters
Description
Value
PLL400_0_TARGET_FREQ
PLL400 #0 target frequency
250 MHz (250000000ul)
PLL400_1_TARGET_FREQ
PLL400 #1 target frequency
196.608 MHz
(196608000ul)
WAIT_FOR_STABILIZATION
Waiting for stabilization
10000ul
PLL400_0_PATH_NO
PLL400 #0 number
1u
PLL400_1_PATH_NO
PLL400 #1 number
2u
CLK_FREQ_ECO
ECO clock frequency
16000000ul (16 MHz)
PATH_SOURCE_CLOCK_FREQ
PATH source clock frequency
CLK_FREQ_ECO
CY_SYSCLK_FLLPLL_OUTPUT_
AUTO
FLL output mode
CY_SYSCLK_FLLPLL_OUTPUT_AUTO:
Automatic using the lock indicator
CY_SYSCLK_FLLPLL_OUTPUT_LOCKED_OR_
NOTHING:
Similar to AUTO, except that the clock is gated
off when unlocked
CY_SYSCLK_FLLPLL_OUTPUT_INPUT:
Selects the FLL reference input (bypass mode)
CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT:
0ul