Infineon TRAVEO T2G family CYT4D Series - Page 37

Application Note 37 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuration of the FLL and PLL
Parameters
Description
Value
manualConfig.lfMode
VCO frequency range selection:
0: VCO frequency is [200 MHz, 400 MHz]
1: VCO frequency is [170 MHz, 200 MHz)
config->lfMode
(Calculated value)
manualConfig.outputMode
Bypass mux located just after PLL output:
0: AUTO
1: LOCKED_OR_NOTHING
2: PLL_REF
3: PLL_OUT
config->outputMode
(Calculated value)
manualConfig.fracDiv
Fractional divider value
config->fracDiv
(Calculated value)
Table 12 List of PLL 200 settings functions
Functions
Description
Value
AllClockConfiguration()
Clock configuration
–
Cy_SysClk_PllConfigure
(PLL Number,PLL Configure)
Set the PLL path number and configure the
PLL (PLL200 #0).
PLL number =
PLL200_0_PATH_NO,
PLL configure =
g_pll200_0_Config
Set the PLL path number and configure the
PLL (PLL200 #1).
PLL number =
PLL200_1_PATH_NO,
PLL configure =
g_pll200_1_Config
Cy_SysLib_DelayUs(Wait
Time)
Delay by the specified number of
microseconds.
Wait time = 1u (1us)
Cy_SysClk_PllManual
Configure(PLL Number, PLL
Manual Configure)
Set the PLL path number and manually
configure the PLL (PLL200 #0).
PLL number =
PLL200_0_PATH_NO,
PLL manual configure =
manualConfig
Set the PLL path number and manually
configure the PLL (PLL200 #1).
PLL number =
PLL200_1_PATH_NO,
PLL manual configure =
manualConfig
Cy_SysClk_GetPllNo
(Clkpath, PllNo)
Return the PLL number according to the
input PATH number (PLL200 #0).
Clkpath = 3u
PllNo = 0u
Return the PLL number according to the
input PATH number (PLL200 #1).
Clkpath = 4u
PllNo = 1u