Infineon TRAVEO T2G family CYT4D Series - Page 36

Application Note 36 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuration of the FLL and PLL
Functions
Description
Value
Cy_SysClk_Pll400M
Enable(PLL Number,Timeout
value)
Set the PLL path number and monitor the
PLL configuration (PLL400 #0).
PLL number =
PLL400_0_PATH_NO,
Timeout value =
WAIT_FOR_STABILIZATION
Set the PLL path number and monitor the
PLL configuration (PLL400 #1).
PLL number =
PLL400_1_PATH_NO,
Timeout value =
WAIT_FOR_STABILIZATION
Table 11 List of PLL 200 settings parameters
Parameters
Description
Value
PLL200_0_TARGET_FREQ
PLL200 #0 target frequency
160 MHz (160000000ul)
PLL200_1_TARGET_FREQ
PLL200 #1 target frequency
80 MHz (80000000ul)
WAIT_FOR_STABILIZATION
Waiting for stabilization
10000ul
PLL200_0_PATH_NO
PLL200 #0 number
3u
PLL200_1_PATH_NO
PLL200 #1 number
4u
PATH_SOURCE_CLOCK_FREQ
PATH source clock frequency
16000000ul (16 MHz)
pllConfig.inputFreq
Input PLL frequency
PATH_SOURCE_CLOCK_
FREQ
pllConfig.outputFreq
Output PLL frequency (PLL200 #0)
PLL200_0_TARGET_FREQ
Output PLL frequency (PLL200 #1)
PLL200_1_TARGET_FREQ
pllConfig.lfMode
PLL LF mode:
0: VCO frequency is [200 MHz, 400 MHz]
1: VCO frequency is [170 MHz, 200 MHz]
0u (VCO frequency is
320 MHz)
pllConfig.outputMode
Output mode:
0: CY_SYSCLK_FLLPLL_OUTPUT_AUTO
1: CY_SYSCLK_FLLPLL_OUTPUT_LOCKED_OR_
NOTHING
2: CY_SYSCLK_FLLPLL_OUTPUT_INPUT
3: CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT
CY_SYSCLK_FLLPLL_
OUTPUT_AUTO
manualConfig.feedbackDiv
Control bits for the feedback divider
p (Calculated value)
manualConfig.referenceDiv
Control bits for the reference divider
q (Calculated value)
manualConfig.outputDiv
Control bits for the output divider:
0: Illegal (undefined behavior)
1: Illegal (undefined behavior)
2: Divide by 2. Suitable for direct usage as the
HFCLK source.
...
16: Divide by 16. Suitable for direct usage as the
HFCLK source.
>16: Illegal (undefined behavior)
out (Calculated value)