Infineon TRAVEO T2G family CYT4D Series - Page 35

Application Note 35 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuration of the FLL and PLL
Parameters
Description
Value
manualConfig.outputMode
Bypass mux located just after PLL output:
0: AUTO
1: LOCKED_OR_NOTHING
2: PLL_REF
3: PLL_OUT
config->outputMode
(Calculated value)
Table 10 List of PLL 400 settings functions
Functions
Description
Value
AllClockConfiguration()
Clock configuration
–
Cy_SysClk_Pll400M
Configure(PLL Number,PLL
Configure)
Set the PLL path number and configure the
PLL (PLL400 #0).
PLL number =
PLL400_0_PATH_NO,
PLL configure =
g_pll400_0_Config
Set the PLL path number and configure the
PLL (PLL400 #1).
PLL number =
PLL400_1_PATH_NO,
PLL configure =
g_pll400_1_Config
Cy_SysClk_Pll400M
Enable(PLL Number, Timeout
value)
Set the PLL path number and monitor the
PLL configuration (PLL400 #0).
PLL number =
PLL400_0_PATH_NO,
Timeout value =
WAIT_FOR_STABILIZATION
Set the PLL path number and monitor the
PLL configuration (PLL400 #1).
PLL number =
PLL400_1_PATH_NO,
Timeout value =
WAIT_FOR_STABILIZATION
Cy_SysLib_DelayUs(Wait
Time)
Delays by the specified number of
microseconds.
Wait time = 1u (1us)
Cy_SysClk_PllManual
Configure(PLL Number, PLL
Manual Configure)
Set the PLL path number and manually
configure the PLL (PLL400 #0).
PLL number =
PLL400_0_PATH_NO,
PLL manual configure =
manualConfig
Set the PLL path number and manually
configure the PLL (PLL400 #1).
PLL number =
PLL400_1_PATH_NO,
PLL manual configure =
manualConfig
Cy_SysClk_GetPll400MNo
(Clkpath, PllNo)
Return the PLL number according to the
input PATH number (PLL400 #0).
Clkpath = 1u
PllNo = 0u
Return the PLL number according to the
input PATH number (PLL400 #1).
Clkpath = 2u
PllNo = 1u
Cy_SysClk_PllCaluc
Dividers()
Calculate the appropriate divider settings
according to the PLL input/output
frequency.