Infineon TRAVEO T2G family CYT4D Series - Page 34

Application Note 34 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuration of the FLL and PLL
Parameters
Description
Value
Selects the FLL output. Ignores then lock
indicator.
See SRSS_CLK_FLL_CONFIG3 in the registers
TRM for details.
pllConfig.inputFreq
Input PLL frequency
PATH_SOURCE_CLOCK_
FREQ
pllConfig.outputFreq
Output PLL frequency (PLL400 #0)
PLL400_0_TARGET_FREQ
Output PLL frequency (PLL400 #1)
PLL400_1_TARGET_FREQ
pllConfig.outputMode
Output mode;
0: CY_SYSCLK_FLLPLL_OUTPUT_AUTO
1: CY_SYSCLK_FLLPLL_OUTPUT_LOCKED_
OR_NOTHING
2: CY_SYSCLK_FLLPLL_OUTPUT_INPUT
3: CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT
CY_SYSCLK_FLLPLL_
OUTPUT_AUTO
pllConfig.fracEn
Enable the fractional divider (PLL400 #0)
false
Enable the fractional divider (PLL400 #1)
true
pllConfig.fracDitherEn
Enable dithering operation (PLL400 #0)
false
Enable dithering operation (PLL400 #1)
true
pllConfig.sscgEn
Enable the SSCG (PLL400 #0)
true
Enable the SSCG (PLL400 #1)
false
pllConfig.sscgDitherEn
Enable SSCG dithering operation (PLL400 #0)
true
Enable SSCG dithering operation (PLL400 #1)
false
pllConfig.sscgDepth
Set the SSCG modulation depth
CY_SYSCLK_SSCG_
DEPTH_MINUS_2_0
pllConfig.sscgRate
Set the SSCG modulation rate
CY_SYSCLK_SSCG_RATE_
DIV_512
manualConfig.feedbackDiv
Control bits for the feedback divider
p (Calculated value)
manualConfig.referenceDiv
Control bits for the reference divider
q (Calculated value)
manualConfig.outputDiv
Control bits for the output divider:
0: Illegal (undefined behavior)
1: Illegal (undefined behavior)
2: Divide by 2. Suitable for direct usage as the
HFCLK source.
...
16: Divide by 16. Suitable for direct usage as the
HFCLK source.
>16: Illegal (undefined behavior)
out (Calculated value)
manualConfig.lfMode
VCO frequency range selection:
0: VCO frequency is [200 MHz, 400 MHz]
1: VCO frequency is [170 MHz, 200 MHz)
config->lfMode
(Calculated value)