Infineon TRAVEO T2G family CYT4D Series - 6.2 Use case of the clock calibration counter function

Application Note 66 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Supplementary information
Table 27 Clock input to SAR ADC
Peripheral function
Operation clock
Unit clock
SAR ADC
CLK_GR9 (Group 9)
Unit0: PCLK (PCLK_PASS_CLOCK_SAR0)
Table 28 Clock input to CXPI
Peripheral function
Operation clock
Channel clock
CXPI
CLK_GR5 (Group 5)
PCLK (PCLK_CXPI0_CLOCK_CH_EN0)
PCLK (PCLK_CXPI0_CLOCK_CH_EN1)
Table 29 Clock input to SMIF
Peripheral function
“clk_slow” domain
(XIP AHB-Lite
Interface0)
“clk_mem”
Domain
(XIP AHB interface)
“clk_sys” domain
(MMIO AHB-Lite
interface)
“clk_if” domain
SMIF
clk_slow
clk_mem
CLK_GR4
CLK_HF6
Table 30 Clock input to AUDIOSS
Peripheral function
clk_sys_i2s
clk_audio_i2s
AUDIOSS
CLK_HF5
CLK_GR8
Note: For details on Ethernet clocks, see the architecture TRM.
6.2 Use case of the clock calibration counter function
The clock calibration counter has two counters that can be used to compare the frequency of two clock
sources. All clock sources are available as a source for these two clocks. For details, see the architecture TRM.
Use the following procedure to calibrate using the clock calibration counter:
1. Calibration Counter1 counts clock pulses from Calibration Clock1 (the high-accuracy clock used as the
reference clock). It counts downwards.
2. Calibration Counter2 counts clock pulses from Calibration Clock2 (measurement clock). It counts upwards.
3. When Calibration Counter1 reaches 0, Calibration Counter2 stops counting upwards, and its value can be
read.
4. The frequency of Calibration Counter2 can be obtained by using its value and the following equation:
CalibrationClock2 =
Counter2value
Counter1value
× CalibrationClock1
Figure 23 shows an example of the clock calibration counter function when ILO0 and ECO are used. ILO0 and
ECO must be enabled. See ILO0 and ECO for 3.4 Configuring ILO0/ILO1 and 3.1 Setting the ECO.