Infineon TRAVEO T2G family CYT4D Series - 4.2.3 Sample code for initial PLL configuration

Application Note 39 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuration of the FLL and PLL
4.2.3 Sample code for the initial PLL configuration
Code Listing 26 to Code Listing 32 show the sample code for the PLL400 #0 example; Code Listing 33 to Code
Listing 39 show the sample code for the PLL200 #0 example.
Code Listing 26 General configuration of PLL 400 #0 settings
:
#define PLL400_0_TARGET_FREQ (250000000ul)
#define PLL400_1_TARGET_FREQ (196608000ul)
:
/** Wait time definition **/
#define WAIT_FOR_STABILIZATION (10000ul)
:
#define PLL_400M_0_PATH_NO (1ul)
#define PLL_400M_1_PATH_NO (2ul)
#define PLL_200M_0_PATH_NO (3ul)
#define PLL_200M_1_PATH_NO (4ul)
#define BYPASSED_PATH_NO (5ul)
:
/*** Parameters for Clock Configuration ***/
cy_stc_pll_400M_config_t g_pll400_0_Config =
{
.inputFreq = PATH_SOURCE_CLOCK_FREQ,
.outputFreq = PLL400_0_TARGET_FREQ,
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
.fracEn = false,
.fracDitherEn = false,
.sscgEn = true,
.sscgDitherEn = true,
.sscgDepth = CY_SYSCLK_SSCG_DEPTH_MINUS_2_0,
.sscgRate = CY_SYSCLK_SSCG_RATE_DIV_512,
};
:
int main(void)
{
:
/* Enable interrupt */
__enable_irq();
/* Set Clock Configuring registers */
AllClockConfiguration();
:
/* Please check clock output using oscilloscope after CPU reached here. */
for(;;);
}
Code Listing 27 AllClockConfiguration() function
static void AllClockConfiguration(void)
{
:
/***** PLL400M#0(PATH1) source setting ******/
{
:
status = Cy_SysClk_Pll400MConfigure(PLL_400M_0_PATH_NO, &g_pll400_0_Config);
CY_ASSERT(status == CY_SYSCLK_SUCCESS);
status = Cy_SysClk_Pll400MEnable(PLL_400M_0_PATH_NO, WAIT_FOR_STABILIZATION);
CY_ASSERT(status == CY_SYSCLK_SUCCESS);
:
}
return;
}
Define the PLL number.
PLL target frequency
Define the TIMEOUT variable.
PLL400 #0 configuration.
PLL400 #0 setting. See Code Listing 27.
PLL400 enable. See Code Listing 32.
PLL400 configuration. See Code Listing 28.