Infineon TRAVEO T2G family CYT4D Series - Page 40

Application Note 40 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuration of the FLL and PLL
Code Listing 28 Cy_SysClk_Pll400MConfigure() function
cy_en_sysclk_status_t Cy_SysClk_Pll400MConfigure(uint32_t clkPath, const cy_stc_pll_400M_config_t *config)
{
/* check for error */
uint32_t pllNo;
cy_en_sysclk_status_t status = Cy_SysClk_GetPll400MNo(clkPath, &pllNo);
if(status != CY_SYSCLK_SUCCESS)
{
return(status);
}
if (SRSS->CLK_PLL400M[pllNo].unCONFIG.stcField.u1ENABLE != 0ul) /* 1 = enabled */
{
return (CY_SYSCLK_INVALID_STATE);
}
cy_stc_pll_400M_manual_config_t manualConfig = {0ul};
const cy_stc_pll_limitation_t* pllLim;
uint32_t fracBitNum;
if(config->fracEn == true)
{
pllLim = &g_limPll400MFrac;
fracBitNum = 24ul;
}
else
{
pllLim = &g_limPll400M;
fracBitNum = 0ul;
}
status = Cy_SysClk_PllCalucDividers(config->inputFreq,
config->outputFreq,
pllLim,
fracBitNum,
&manualConfig.feedbackDiv,
&manualConfig.referenceDiv,
&manualConfig.outputDiv,
&manualConfig.fracDiv
);
if(status != CY_SYSCLK_SUCCESS)
{
return(status);
}
manualConfig.outputMode = config->outputMode;
manualConfig.fracEn = config->fracEn;
manualConfig.fracDitherEn = config->fracDitherEn;
manualConfig.sscgEn = config->sscgEn;
manualConfig.sscgDitherEn = config->sscgDitherEn;
manualConfig.sscgDepth = config->sscgDepth;
manualConfig.sscgRate = config->sscgRate;
status = Cy_SysClk_Pll400MManualConfigure(clkPath, &manualConfig);
return (status);
}
Code Listing 29 Cy_SysClk_Pll400MManualConfigure() function
cy_en_sysclk_status_t Cy_SysClk_Pll400MManualConfigure(uint32_t clkPath, const cy_stc_pll_400M_manual_config_t
*config)
{
/* check for error */
uint32_t pllNo;
cy_en_sysclk_status_t status = Cy_SysClk_GetPll400MNo(clkPath, &pllNo);
if(status != CY_SYSCLK_SUCCESS)
{
return(status);
}
/* valid divider bitfield values */
if((config->outputDiv < PLL_400M_MIN_OUTPUT_DIV) || (PLL_400M_MAX_OUTPUT_DIV < config->outputDiv))
{
return(CY_SYSCLK_BAD_PARAM);
}
if((config->referenceDiv < PLL_400M_MIN_REF_DIV) || (PLL_400M_MAX_REF_DIV < config->referenceDiv))
{
return(CY_SYSCLK_BAD_PARAM);
}
Check for valid clock path and PLL400
number. See Code Listing 30.
(1) Check if PLL400 is already enabled.
PLL400 manual configuration. See Code Listing 29.
Get the PLL400 PATH number. See Code Listing 30.