Infineon TRAVEO T2G family CYT4D Series - Page 41

Application Note 41 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuration of the FLL and PLL
Code Listing 29 Cy_SysClk_Pll400MManualConfigure() function
if((config->feedbackDiv < PLL_400M_MIN_FB_DIV) || (PLL_400M_MAX_FB_DIV < config->feedbackDiv))
{
return(CY_SYSCLK_BAD_PARAM);
}
un_CLK_PLL400M_CONFIG_t tempClkPLL400MConfigReg;
tempClkPLL400MConfigReg.u32Register = SRSS->CLK_PLL400M[pllNo].unCONFIG.u32Register;
if (tempClkPLL400MConfigReg.stcField.u1ENABLE != 0ul) /* 1 = enabled */
{
return(CY_SYSCLK_INVALID_STATE);
}
/* no errors */
/* If output mode is bypass (input routed directly to output), then done.
The output frequency equals the input frequency regardless of the frequency parameters. */
if (config->outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT)
{
tempClkPLL400MConfigReg.stcField.u8FEEDBACK_DIV = (uint32_t)config->feedbackDiv;
tempClkPLL400MConfigReg.stcField.u5REFERENCE_DIV = (uint32_t)config->referenceDiv;
tempClkPLL400MConfigReg.stcField.u5OUTPUT_DIV = (uint32_t)config->outputDiv;
}
tempClkPLL400MConfigReg.stcField.u2BYPASS_SEL = (uint32_t)config->outputMode;
SRSS->CLK_PLL400M[pllNo].unCONFIG.u32Register = tempClkPLL400MConfigReg.u32Register;
un_CLK_PLL400M_CONFIG2_t tempClkPLL400MConfig2Reg;
tempClkPLL400MConfig2Reg.u32Register = SRSS->CLK_PLL400M[pllNo].unCONFIG2.u32Register;
tempClkPLL400MConfig2Reg.stcField.u24FRAC_DIV = config->fracDiv;
tempClkPLL400MConfig2Reg.stcField.u3FRAC_DITHER_EN = config->fracDitherEn;
tempClkPLL400MConfig2Reg.stcField.u1FRAC_EN = config->fracEn;
SRSS->CLK_PLL400M[pllNo].unCONFIG2.u32Register = tempClkPLL400MConfig2Reg.u32Register;
un_CLK_PLL400M_CONFIG3_t tempClkPLL400MConfig3Reg;
tempClkPLL400MConfig3Reg.u32Register = SRSS->CLK_PLL400M[pllNo].unCONFIG3.u32Register;
tempClkPLL400MConfig3Reg.stcField.u10SSCG_DEPTH = (uint32_t)config->sscgDepth;
tempClkPLL400MConfig3Reg.stcField.u3SSCG_RATE = (uint32_t)config->sscgRate;
tempClkPLL400MConfig3Reg.stcField.u1SSCG_DITHER_EN = (uint32_t)config->sscgDitherEn;
tempClkPLL400MConfig3Reg.stcField.u1SSCG_EN = (uint32_t)config->sscgEn;
SRSS->CLK_PLL400M[pllNo].unCONFIG3.u32Register = tempClkPLL400MConfig3Reg.u32Register;
return (CY_SYSCLK_SUCCESS);
}
Code Listing 30 Cy_SysClk_GetPll400MNo() function
__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_GetPll400MNo(uint32_t pathNo, uint32_t* pllNo)
{
/* check for error */
if ((pathNo <= 0ul) || (pathNo > SRSS_NUM_PLL400M))
{
/* invalid clock path number */
return(CY_SYSCLK_BAD_PARAM);
}
*pllNo = pathNo - 1ul;
return(CY_SYSCLK_SUCCESS);
}
Code Listing 31 Cy_SysClk_PllCalucDividers() function
__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PllCalucDividers(uint32_t inFreq,
uint32_t targetOutFreq,
const cy_stc_pll_limitation_t* lim,
uint32_t fracBitNum,
uint32_t* feedBackDiv,
uint32_t* refDiv,
uint32_t* outputDiv,
uint32_t* feedBackFracDiv)
{
uint64_t errorMin = 0xFFFFFFFFFFFFFFFFull;
if(feedBackDiv == NULL)
{
return (CY_SYSCLK_BAD_PARAM);
}
if((feedBackFracDiv == NULL) && (fracBitNum != 0ul))
(3) Fractional divider settings
(4) SSCG settings
(2) PLL400 configuration