Infineon TRAVEO T2G family CYT4D Series - Page 47

Application Note 47 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuration of the FLL and PLL
Code Listing 39 Cy_SysClk_PllEnable() function
cy_en_sysclk_status_t Cy_SysClk_PllEnable(uint32_t clkPath, uint32_t timeoutus)
{
uint32_t pllNo;
cy_en_sysclk_status_t status = Cy_SysClk_GetPllNo(clkPath, &pllNo);
if(status != CY_SYSCLK_SUCCESS)
{
return(status);
}
/* first set the PLL enable bit */
SRSS->unCLK_PLL_CONFIG[pllNo].stcField.u1ENABLE = 1ul;
/* now do the timeout wait for PLL_STATUS, bit LOCKED */
for (; (SRSS->unCLK_PLL_STATUS[pllNo].stcField.u1LOCKED == 0ul) &&
(timeoutus != 0ul);
timeoutus--)
{
Cy_SysLib_DelayUs(1u);
}
status = ((timeoutus == 0ul) ? CY_SYSCLK_TIMEOUT : CY_SYSCLK_SUCCESS);
return (status);
}
(10) Enable PLL200
(11) Wait until PLL200 is locked.
Wait for 1 us.
(12) Check the timeout.