Infineon TRAVEO T2G family CYT4D Series - Page 38

Application Note 38 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuration of the FLL and PLL
Functions
Description
Value
Cy_SysClk_PllCaluc
Dividers(InputFreq,
OutputFreq,PLLlimit,FracBi
tNum,RefDiv,OutputDiv,Feed
BackFracDiv)
Calculate the appropriate divider settings
according to the PLL input/output
frequency.
InputFreq =
PATH_SOURCE_CLOCK_
FREQ
OutputFreq =
PLL400_0_TARGET_FREQ
(PLL 400 #0),
PLL400_1_TARGET_FREQ
(PLL 400 #1),
PLL200_0_TARGET_FREQ
(PLL 200 #0),
PLL200_1_TARGET_FREQ
(PLL 200 #1)
PLLlimit =
g_limPll400MFrac (PLL 400
#1 only),
g_limPll400M (Other)
FracBitNum =
24ul (PLL 400 #1 only),
0ul (Other)
FeedBackDiv =
manualConfig.feedbackDiv
RefDiv =
manualConfig.referenceDiv
OutputDiv =
manualConfig.outputDiv
FeedBackFracDiv =
manualConfig.fracDiv
Cy_SysClk_PllEnable(PLL
Number, Timeout value)
Set the PLL path number and monitor the
PLL configuration (PLL200 #0).
PLL number =
PLL200_0_PATH_NO,
Timeout value =
WAIT_FOR_STABILIZATION
Set the PLL path number and monitor the
PLL configuration (PLL200 #1).
PLL number =
PLL200_1_PATH_NO,
Timeout value =
WAIT_FOR_STABILIZATION