Infineon TRAVEO T2G family CYT4D Series - Page 32

Application Note 32 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuration of the FLL and PLL
Start
Yes
Wait until PLL200M is locked?
No
PLL200M configuration
Enable PLL200M
Based on the specification of the application,
configure PLL200M to each register.
End(Success) End(Timeout)
TIMEOUT?
Yes
No
PLL200M already enabled?
No
Yes
End(No Change)
Case: PLL400
Case: PLL200
PLL400M already enabled?
No
Yes
Fractional divider setting
Enable fractional divider
Use Fractional Divider ?
Yes
No
SSCG setting
Enable SSCG
Use SSCG?
Yes
No
Yes
Wait until PLL400M is locked ?
No
Enable PLL400M.
End(Success)
End(Timeout)
TIMEOUT?
Yes
No
End(No Change)
Start
Fractional divider settings
SSCG settings
PLL400M configuration
Based on the specification of the application,
configure PLL400M to each register.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
Figure 13 Procedure for configuring the PLL