EasyManua.ls Logo

Infineon TRAVEO T2G family CYT4D Series - Page 5

Infineon TRAVEO T2G family CYT4D Series
80 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
Application Note 5 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Clock system for TRAVEO™ T2G family MCUs
supported clock resources, FLL, and PLL to generate the required high-speed clocks. These MCUs support two
types of PLLs: PLL without spread spectrum clock generation (SSCG) and fractional operation (PLL200#x), and
PLL with SSCG and fractional operation (PLL400#x).
Figure 2 Block diagram

Table of Contents