Infineon TRAVEO T2G family CYT4D Series - Page 72

Application Note 72 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Supplementary information
Code Listing 64 Cy_SysClk_IloTrim() function
int32_t Cy_SysClk_IloTrim(uint32_t iloFreq, uint8_t iloNo)
{
/* Nominal trim step size is 1.5% of "the frequency". Using the target frequency. */
const uint32_t trimStep = CY_SYSCLK_DIV_ROUND((uint32_t)CY_SYSCLK_ILO_TARGET_FREQ * 15ul, 1000ul);
uint32_t newTrim = 0ul;
uint32_t curTrim = 0ul;
/* Do nothing if iloFreq is already within one trim step from the target */
uint32_t diff = (uint32_t)abs((int32_t)iloFreq - (int32_t)CY_SYSCLK_ILO_TARGET_FREQ);
if (diff >= trimStep)
{
if(iloNo == 0u)
{
curTrim = SRSS->unCLK_TRIM_ILO0_CTL.stcField.u6ILO0_FTRIM;
}
else
{
curTrim = SRSS->unCLK_TRIM_ILO1_CTL.stcField.u6ILO1_FTRIM;
}
if (iloFreq > CY_SYSCLK_ILO_TARGET_FREQ)
{ /* iloFreq is too high. Reduce the trim value */
newTrim = curTrim - CY_SYSCLK_DIV_ROUND(iloFreq - CY_SYSCLK_ILO_TARGET_FREQ, trimStep);
}
else
{ /* iloFreq too low. Increase the trim value. */
newTrim = curTrim + CY_SYSCLK_DIV_ROUND(CY_SYSCLK_ILO_TARGET_FREQ - iloFreq, trimStep);
}
/* Update the trim value */
if(iloNo == 0u)
{
if(WDT->unLOCK.stcField.u2WDT_LOCK != 0ul) /* WDT registers are disabled */
{
return(CY_SYSCLK_INVALID_STATE);
}
SRSS->unCLK_TRIM_ILO0_CTL.stcField.u6ILO0_FTRIM = newTrim;
}
else
{
SRSS->unCLK_TRIM_ILO1_CTL.stcField.u6ILO1_FTRIM = newTrim;
}
}
return (int32_t)(curTrim - newTrim);
}
(3) Calculate the trimming step.
(4) Calculate the diff between current and
target.
frequency
Check if the current frequency is smaller than the target frequency.
(6) Calculate the
new trim value.
Check if the watchdog timer disabled.
Check if diff is greater than the trimming step.
(7) Set the new trimming value.
(5) Read the current trimming value.