Intel Agilex

Figure 1. Fixed-Point Arithmetic 9 x 9 Mode
Input Register Bank
LOADCONST
ACCUMULATE
ay[8..0]
ax[8..0]
by[8..0]
bx[8..0]
+
+
1st Multiplier
Chainout adder
+
Output Register Bank
Double
Accumulation
Register
chainin[63..0]
chainout[63..0]
resulta[36:0]
3rd Multiplier
x
CLK
ENA[2..0]
CLR[1..0]
*1st Pipleine Register
*2nd Pipleine Register
*This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block.
1 0
DISABLE_CHAINOUT
64’b0
Constant
x
x
x
cy[8..0]
cx[8..0]
dy[8..0]
dx[8..0]
+
2nd Multiplier
4th Multiplier
1st Adder
2nd Adder
Adder
2. Intel Agilex Variable Precision DSP Blocks Architecture
UG-20213 | 2019.04.02
Intel
®
Agilex
™
Variable Precision DSP Blocks User Guide
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