Intel Agilex

The floating-point adder or subtract mode supports the following exception flags:
•
fp32_adder_invalid
•
fp32_adder_inexact
•
fp32_adder_overflow
•
fp32_adder_underflow
Figure 29. Adder or Subtract Mode for Intel Agilex
fp32_chainout[31:0]
fp32_chainin[31:0]
accumulate
fp32_adder_a[31:0]
fp32_adder_b[31:0]
fp32_mult_a[31:0]
Output
Register
Bank
Input
Register
Bank
fp32_result[31:0]
Multiplier
Adder
*Pipeline
Register
Bank
Register
Bank
*Pipeline
Register
Bank
fp32_adder_invalid
fp32_adder_inexact
fp32_adder_overflow
fp32_adder_underflow
*Pipeline
Pipeline
Register
Bank
Pipeline
Register
Bank
*This block diagram shows the functional representation of the DSP block.
The pipeline registers are embedded within the various circuits of the DSP block.
fp32_mult_b[31:0]
3.2.1.3. Multiply Accumulate Mode
This mode performs floating-point multiplication followed by floating-point addition or
subtraction with the previous multiplication result.
When ACCUMULATE signal is high, this mode uses the equation of fp32_result(t) =
[fp32_mult_a(t-1)*fp32_mult_b(t-1)] +/- fp32_result(t-1).
When ACCUMULATE signal is low, this mode uses the equation of fp32_result =
(ay*az).
The floating-point multiply accumulate mode supports the following exception flags:
•
fp32_mult_invalid
•
fp32_mult_inexact
•
fp32_mult_overflow
•
fp32_mult_underflow
•
fp32_adder_invalid
•
fp32_adder_inexact
•
fp32_adder_overflow
•
fp32_adder_underflow
3. Intel Agilex Variable Precision DSP Blocks Operational Modes
UG-20213 | 2019.04.02
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Variable Precision DSP Blocks User Guide
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