Intel Agilex User Guide

Figure 30. Multiply Accumulate Mode for Intel Agilex Devices
fp32_chainout[31:0]
fp32_chainin[31:0]
accumulate
fp32_adder_a[31:0]
fp32_mult_a[31:0]
fp32_mult_b[31:0]
Output
Register
Bank
Input
Register
Bank
fp32_result[31:0]
Multiplier
Adder
*Pipeline
Register
Bank
Register
Bank
*Pipeline
Register
Bank
*Pipeline
Register
Bank
fp32_mult_invalid
fp32_mult_inexact
fp32_mult_overflow
fp32_mult_underflow
fp32_adder_inexact
fp32_adder_invalid
fp32_adder_overflow
fp32_adder_underflow
*Pipeline
Register
Bank
*Pipeline
*This block diagram shows the functional representation of the DSP block.
The pipeline registers are embedded within the various circuits of the DSP block.
fp32_adder_b[31:0]
3.2.1.4. FP32 Vector One Mode
This mode performs floating-point multiplication followed by floating-point addition or
subtraction with the chainin input from the previous variable DSP Block. Input
fp32_adder_a is directly fed into chainout.
Table 16. Equations Applied to FP32 Vector One Mode
Chainin Parameter Vector One with Floating-Point
Addition
Vector One with Floating-Point
Subtraction
Disable
result = fp32_mult_a *
fp32_mult_b
Chainout = fp32_adder_a
result = fp32_mult_a *
fp32_mult_b
Chainout = fp32_adder_a
Enable
result = (fp32_mult_a *
fp32_mult_b) + fp32_chainin
Chainout = fp32_adder_a
result = (fp32_mult_a *
fp32_mult_b) - fp32_chainin
Chainout = fp32_adder_a
The FP32 vector one mode supports the following exception flags:
•
fp32_mult_invalid
•
fp32_mult_inexact
•
fp32_mult_overflow
•
fp32_mult_underflow
•
fp32_adder_invalid
•
fp32_adder_inexact
•
fp32_adder_overflow
•
fp32_adder_underflow
3. Intel Agilex Variable Precision DSP Blocks Operational Modes
UG-20213 | 2019.04.02
Intel
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Variable Precision DSP Blocks User Guide
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Intel Agilex Specifications

General

Brand	Intel
Model	Agilex
Category	Microcontrollers
Language	English