Intel Agilex - Page 47

3.2.2.3. Sum of Two FP16 Multiplication with FP32 Addition Mode
This mode performs a summation of two half-precision multiplication, provide a 32-bit
result, and add with a single-precision number:
fp32_result = (fp16_mult_top_a*fp16_mult_top_b) +
(fp16_mult_bot_a*fp16_mult_bot_b) + fp32_adder_a
The following are exception flags supported in flushed and bfloat16 formats:
•
fp16_mult_top_invalid
•
fp16_mult_top_inexact
•
fp16_mult_top_overflow
•
fp16_mult_top_underflow
•
fp16_mult_bot_invalid
•
fp16_mult_bot_inexact
•
fp16_mult_bot_overflow
•
fp16_mult_bot_underflow
•
fp16_adder_invalid
•
fp16_adder_inexact
•
fp16_adder_overflow
•
fp16_adder_underflow
•
fp32_adder_invalid
•
fp32_adder_inexact
•
fp32_adder_overflow
•
fp32_adder_underflow
The following are exception flags supported in extended format:
•
fp16_mult_top_invalid
•
fp16_mult_top_inexact
•
fp16_mult_top_infinite
•
fp16_mult_top_zero
•
fp16_mult_bot_invalid
•
fp16_mult_bot_inexact
•
fp16_mult_bot_infinite
•
fp16_mult_bot_zero
•
fp16_adder_invalid
•
fp16_adder_inexact
•
fp16_adder_infinite
•
fp16_adder_zero
•
fp32_adder_invalid
3. Intel Agilex Variable Precision DSP Blocks Operational Modes
UG-20213 | 2019.04.02
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