EasyManuals Logo

Intel Agilex User Guide

Intel Agilex
73 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #51 background imageLoading...
Page #51 background image
fp16_mult_bot_infinite
fp16_mult_bot_zero
fp16_adder_invalid
fp16_adder_inexact
fp16_adder_infinite
fp16_adder_zero
fp32_adder_invalid
fp32_adder_inexact
fp32_adder_overflow
fp32_adder_underflow
Figure 36. FP16 Vector One Mode
fp32_chainout[31:0]
fp32_chainin[31:0]
fp32_adder_a[31:0]
fp16_mult_top_a[15:0]
fp32_result[31:0]
Input
Register
Bank
Top
Multiplier
Adder
*Pipeline
Register
*Pipeline
Register
*Pipeline
Register
*Pipeline
Register
*Pipeline
Register
Output
Register
Bank
*This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block.
fp16_mult_top_b[15:0]
fp16_mult_bot_a[15:0]
Bottom
Multiplier
fp16_mult_bot_b[15:0]
*Pipeline
Register
Register
Adder
fp16_mult_top_invalid
fp16_mult_top_underflow
fp16_mult_top_overflow
fp32_adder_invalid
fp32_adder_inexact
fp32_adder_overflow
fp32_adder_underflow
fp16_mult_top_inexact
fp16_mult_bot_invalid
fp16_mult_bot_underflow
fp16_mult_bot_overflow
fp16_mult_bot_inexact
fp16_adder_invalid
fp16_adder_inexact
fp16_adder_overflow
fp16_adder_underflow
fp16_mult_top_infinite(extended format)
fp16_mult_top_zero(extended format)
fp16_mult_bot_infinite(extended format)
fp16_mult_bot_zero(extended format)
fp16_adder_infinite(extended format)
fp16_adder_zero(extended format)
3.2.2.6. FP16 Vector Two Mode
This mode performs a summation of two half precision multiplication and fed to
chainout. The chainin input from the previous variable DSP Block is then added or
subtracted from input fp32_adder_a as the output result.
Table 20. Equations Applied to FP16 Vector Two Mode
Chainin Parameter Vector Two with Floating-Point
Addition
Vector Two with Floating-Point
Subtraction
Disable
fp32_result = fp32_adder_a
fp32_chainout = (fp16_mult_top_a
* fp16_mult_top_b) +
(fp16_mult_bot_a *
fp16_mult_bot_b)
fp32_result = fp32_adder_a
fp32_chainout = (fp16_mult_top_a
* fp16_mult_top_b) -
(fp16_mult_bot_a *
fp16_mult_bot_b)
Enable
fp32_result = fp32_adder_a +
fp32_chainin
fp32_result = fp32_adder_a -
fp32_chainin
continued...
3. Intel Agilex Variable Precision DSP Blocks Operational Modes
UG-20213 | 2019.04.02
Send Feedback
Intel
®
Agilex
Variable Precision DSP Blocks User Guide
51

Table of Contents

Other manuals for Intel Agilex

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Intel Agilex and is the answer not in the manual?

Intel Agilex Specifications

General IconGeneral
BrandIntel
ModelAgilex
CategoryMicrocontrollers
LanguageEnglish

Related product manuals