After successful FPGA configuration, the appropriate tab appears that allows you to
exercise the related board features.
The Power Monitor button starts the Power Monitor application that measures and
reports current power information for the board. Because the application
communicates over the JTAG bus to the MAX II device, you can measure the power of
any design in the FPGA, including your own designs.
Attention: The Board Test System and Power Monitor share the JTAG bus with other applications
like the Nios
®
II debugger and the Signal Tap logic analyzer. Because the Quartus
Prime programmer uses most of the bandwidth of the JTAG bus, other applications
using the JTAG bus might time out. Be sure to close the other applications before
attempting to reconfigure the FPGA using the Quartus Prime Programmer.
5.1. Preparing the Board for the Board Test System
With the power to the board off, follow these steps:
1. Plug the included USB cable from J37 (Intel FPGA Download Cable II interface) to
the host computer's USB port.
2. Ensure that the development board switches and jumpers are set to the default
positions as shown in the Factory Default Switch and Jumper Settings section.
For more information about the board’s DIP switch and jumper settings, refer to
the Cyclone V SoC Development Board Reference Manual.
Caution: To ensure operating stability, keep the USB cable connected and the board powered on
when running the demonstration application. The application cannot run correctly
unless the USB cable is attached and the board is on.
Related Information
• Factory Default Switch and Jumper Settings on page 15
• Cyclone V SoC Development Board Reference Manual
5.2. Running the Board Test System
Navigate to the cycloneVSX_5csxfc6df31_soc\examples\board_test_system
directory and double click the BoardTestSystem.bat.
A GUI appears, displaying the application tab that corresponds to the design running
in the FPGA. Typically, the board is not pre-programmed with a BTS design. You must
load using the Configure menu as described in the next section.
5. Board Test System
830285 | 2024.10.07
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