Intel altera Cyclone V SoC - Feature Summary

1.2. Feature Summary
Device
• Cyclone V SX SoC—5CSXFC6D6F31C6N (SoC)
• MAX
®
V CPLD—5M2210ZF256C4N (system controller)
• MAX II CPLD—EPM570GF100 (embedded Intel
®
FPGA Download Cable II)
FPGA I/O Interfaces
• 2 10/100 Megabit Ethernet PHYs (EtherCAT)
• PCIe* 1.0 x4 female connector
• Universal high-speed mezzanine card (HSMC)—x4 transceivers, x16 TX LVDS, x16
RX LVDS
• 1 serial digital interface (SDI) channel
• 4 SMAs for one transceiver channel
• 4 push buttons
• 2 switches
• 4 LEDs
HPS I/O Interfaces
• 1 USB 2.0 On-the-Go (OTG)
• 1 10/100/1000 Megabit Ethernet (10MbE/100MbE/1000MbE)
• 1 CAN
• 1 UART (UART to USB bridge)
• 1 real-time clock (with battery backup)
• 1 two-line text LCD
• 1-/2-channel, 20 bit delta-sigma analog-to-digital converter (Linear Technology
LTC2422)
• 4 push buttons
• 4 switches
• 4 LEDs
HPS Boot Sources
• 1 GB DDR3 SDRAM (32 bit) with error correction code (ECC)
• 128 MB quad SPI flash memory
• Micro-SD card socket with 4 GB micro-SD card flash device
1. Overview
830285 | 2024.10.07
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Cyclone
®
V SoC Development Kit User Guide
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