Intel altera Cyclone V SoC - Block Diagram

1.1. Block Diagram
Figure 3. Cyclone V SoC Development Kit Block Diagram
MAX® V
On-Board Intel® FPGA
Download Cable II
and USB interface
x19 Blaster
Accelerator Bus
Mini-USB
2.0
JTAG Chain
LED
(3:0)
DIPSW
(3:0)
PB
(3:0)
USB2
OTG
UART CAN
Real-Time
Clock
EEPROM
LTC Power
Monitor
SPI + I2C
LTC Exp Hdr
I2C
1024 MB
DDR3 + ECC
x40
1024 MB
QSPI Flash
x4
SD Card
Socket
x4
GbE
PHY
x16
LTC Power
I2C Header
Cyclone® V SoC
(5CSXFC6D6F31C6N)
®
HPS
FPGA
x4 x4 x4 x8 x1 x1
Character
LCD
x1
x4
x2
x40
MAX® V
CPLD
128 MB
NOR FLASH
PCI Express*
x4
HSMC
Port A
SDI
x1
SMA
ADDR
x16
x8 Config
x80
XC VR x4
CLKIN x3
XC VR x4
CLKOUT x3
x8
XC VR x1
x1
x4
x4
x1
x4
x1
1024 MB
DDR3 + ECC
DIPSW
50M/100M
Fixed OSC
10/100
Ethernet
10/100
Ethernet
REFCLK
VCXO
PB
LED
Legend:
1. Overview
830285 | 2024.10.07
Cyclone
®
V SoC Development Kit User Guide
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