JTAG Chain
The JTAG chain control shows all the devices currently in the JTAG chain. The
Cyclone V device is always the first device in the chain. The JTAG chain is normally
mastered by the onboard Intel FPGA Download Cable II.
Note: If you plug in an external onboard Intel FPGA Download Cable cable to the JTAG
header (J23), the onboard Intel FPGA Download Cable II is disabled.
Note: JTAG DIP switch bank (SW4) selects which interfaces are in the chain. Refer to the
SW4 JTAG DIP Switch Settings table in the Factory Default Switch and Jumper
Settings section for detailed settings.
For details on the JTAG chain, refer to the Cyclone V SoC Development Board
Reference Manual. For Intel FPGA Download Cable II configuration details, refer to the
Cable and Adapter Drivers Information webpage of the Intel website.
Related Information
• Factory Default Switch and Jumper Settings on page 15
• Cyclone V SoC Development Board Reference Manual
5. Board Test System
830285 | 2024.10.07
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