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Intel altera Cyclone V SoC - Page 36

Intel altera Cyclone V SoC
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Inserted errors: Displays the number of errors inserted by clicking Insert Error
button.
Detected errors: Displays the number of bit errors detected by the error
checking circuitry.
BER: Displays the bit error rate of the interface.
PLL lock: Displays Yes if the SDI PLL is locked.
Pattern Sync: Displays Yes if the receiver has detected the input data pattern.
Start: Starts the PRBS data test and begins to monitor and update screen with
live test results.
Stop: Stops the PRBS data test.
Insert Error: Inserts an error into an SDI data stream that is detected by the
receiver when in loopback using the included video cable.
Clear: Clears the Detected errors counter.
PMA Setting: Opens the PMA settings window that allows for adjusting the
analog transceiver settings, such as output voltage, loopback settings, and
equalization.
PRBS (list): Selects the transmit pattern and sets the receive error detection
circuitry to expect the same pattern for use in loopback testing.
5. Board Test System
830285 | 2024.10.07
Cyclone
®
V SoC Development Kit User Guide
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