EasyManua.ls Logo

Intel altera Cyclone V SoC - Page 38

Intel altera Cyclone V SoC
58 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
Detected errors: Displays the number of bit errors detected by the error
checking circuitry.
BER: Displays the bit error rate of the interface.
PLL lock: Displays Yes if the SDI PLL is locked.
Pattern Sync: Displays Yes if the receiver has detected the input data pattern.
Start: Starts the PRBS data test and begins to monitor and update screen with
live test results.
Stop: Stops the PRBS data test.
Insert Error: Inserts an error into a data stream that is detected by the receiver
when in loopback using the included video cable.
With the Insert Error, there are differences among the three ports:
XCVR: inserts 4 errors at 1 click due to 4 test control blocks in the design.
LVDS: inserts 3 errors at 1 click due to 3 test control blocks in the design.
CMOS: inserts 1 error at 1 click.
Clear: Clears the Detected errors counter.
PMA Setting: Opens the PMA settings window that allows for adjusting the
analog transceiver settings, such as output voltage, loopback settings, and
equalization.
The following settings are available for analysis:
Serial Loopback: Routes the selected TX output signal back to the RX input
signal on-chip to verify operation without using an external loopback board.
VOD: Specifies the voltage output (differential) of the transmitter buffer.
Pre-emphasis tap
Pre: Specifies the amount of pre-emphasis on the pre-tap of the
transmitter buffer.
First post: Specifies the amount of pre-emphasis on the first post tap of
the transmitter buffer.
Second post: Specifies the amount of pre-emphasis on the second post
tap of the transmitter buffer.
Attention: Support for this tap is device and software version dependent.
Equalizer: Specifies the setting for the receiver equalizer.
DC gain: Specifies the DC portion of the receiver equalizer.
PRBS: Selects the transmit pattern and sets the receive error detection circuitry
to expect the same pattern for use in loopback testing.
5. Board Test System
830285 | 2024.10.07
Cyclone
®
V SoC Development Kit User Guide
Send Feedback
38

Table of Contents

Related product manuals