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Intel Confidential
Descriptor Overview
26:24
Write and Erase Clock Frequency.
000 = 20 MHz
001 = 33 MHz
100 = 50 MHz
All other Settings = Reserved
Notes:
1.If more than one Flash component exists, this field must be set to the lowest common frequency
of the different Flash components.
2.If setting to 50 MHz, ensure flash meets timing requirements defined in Table 3-3
23:21
Fast Read Clock Frequency. This field identifies the frequency that can be used with the Fast Read
instruction. This field is undefined if the Fast Read Support field is '0'.
000 = 20 MHz
001 = 33 MHz
100 = 50 MHz
All other Settings = Reserved
Notes:
1.If more than one Flash component exists, this field must be set to the lowest common frequency
of the different Flash components.
2.If setting to 50 MHz, ensure flash meets timing requirements defined in Table 3-3
20
Fast Read Support.
0 = Fast Read is not Supported
1 = Fast Read is supported
If the Fast Read Support bit is a '1' and a device issues a Direct Read or issues a read command from
the Hardware Sequencer and the length is greater than 4 bytes, then the SPI Flash instruction
should be "Fast Read”. If the Fast Read Support is a '0' or the length is 1-4 bytes, then the SPI Flash
instruction should be “Read”.
Reads to the Flash Descriptor always use the Read command independent of the setting of this bit.
Notes:
1.If more than one Flash component exists, this field can only be set to '1' if both components
support Fast Read.
2.It is strongly recommended to set this bit to 1b
19:17
Read Clock Frequency.
000 = 20 MHz
All other Settings = Reserved
Note:
1.If more than one Flash component exists, this field must be set to the lowest common frequency
of the different Flash components.
Bits Description
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