Intel Pentium III - Terminator-Less T Topology; Terminator-Less System Bus T Topology

3-4 Intel
®
Pentium
®
III Processor with 512KB L2 Cache Dual Processor Platform Design Guide
3.3 Terminator-less T Topology
For dual processor platform designs without a terminator, the following new T topology is recommended.
A new segment (L3) with a pull-up resistor to Vtt has been added to provide termination when the CPU1
socket is not populated. The L3 segment should be connected as close to the CPU1 pin as possible,
preferably after the L1 segment connects to the CPU1 pin. The R4 value for CPU1 uses a 100Ω resistor
pulled down to Vss instead of the 68Ω that is normally recommended. CPU0's R3 value should remain
68Ω.
Please Note: Intel will not be validating the terminator-less T topology design. This design is based
on extensive simulation results that have been performed by Intel. It is provided as a reference for
designs seeking to not require a terminator when the system is operating with one processor. Intel
recommends that any implementation of this topology be simulated and validated carefully.
Figure 3-2. Terminator-less System Bus T Topology
Chipset
CPU0
CPU1 or
Terminator
L0 L1
L2
L3
V
TT
R1 R2
V
TT
R5
V
TT
RTTCTRL
R3
RTTCTRL
R4