Intel
®
Pentium
®
III Processor with 512KB L2 Cache Dual Processor Platform Design Guide 3-7
3.5 Simulation Methodology
Analog simulations are recommended for high-speed system bus designs. Start simulations prior to
layout. Pre-layout simulations provide a detailed picture of the working “solution space” that meets flight
time and signal quality requirements. By basing board layout guidelines on the solution space, the
iterations between layout and post-layout simulations can be reduced.
Intel recommends running simulations at the device pads for signal quality and at the device pins for
timing analysis. However, simulation results at the device pins may be used later to correlate simulation
performance against actual system measurements.
Intel
®
Pentium
®
III Processor with 512KB L2 Cache DP I/O buffer models are available from the Intel
Developer website.
3.6 Trace Routing
The following guidelines should be followed when routing the AGTL host bus signal traces:
• Traces should have an impedance of 60Ω +/- 15%
• The nominal trace width should be 5 mils.
• The L0 and L1 lengths in Table 3-5 should be matched to within 0.25 inches.
• Minimize the number of vias and layer transitions.
3.7 Layout Rules for AGTL Signals
3.7.1 Ground Reference
It is strongly recommended that AGTL signals be routed on the signal layer next to the ground layer
(referenced to ground). It is important to provide effective signal return path with low inductance. The
best signal routing is directly adjacent to a solid GND plane with no splits or cuts. Eliminate parallel
traces between layers not separated by a power or ground plane.
3.7.2 Reference Plane Splits
Splits in reference planes disrupt signal return paths and increase overshoot/undershoot due to
significantly increased inductance. For optimal signal integrity, high-speed signals should not be routed
over power plane splits.
3.7.3 CPU Connector Breakout
It is strongly recommended that AGTL signals do not traverse multiple signal layers. Intel recommends
breaking out all signals from the connector on the same layer. If routing is tight, breakout from the
connector on the opposite routing layer over a ground reference and cross over to main signal layer near
the CPU connector.
Note: Following the above layout rules is critical for AGTL signal integrity.
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